![]() ![]() But before we look at the actual implementation, let’s review the derived layer concept. In ADS 2012.08, Agilent introduced the derived layer function “grow envelope” that we can use for via merging. Via simplification by ADS 2012 derived layers Too large values might create false connections (short circuit) between adjacent via arrays. used larger values for oversize/undersize, within reasonable limits. This is relevant for via simplification algorithms that are based on exact viasize and viaspacing values: better add some tolerance to handle these cases, i.e. The viasize or viaspacing might be slightly increased to match the total dimension. What values should we use for oversize/undersize? Depending on the foundry and PDK implementation, there are subtle differences how Pcells generate via arrays with a given target size that doesn’t match exactly with n*viasize + (n-1)*viaspacing. This can be automated by an AEL script, as shown here: Then, the overlapping shapes are merged, and finally the merged shape is undersized again, so that we get back to the original outline. The vias of an array can be merged by a series of oversize – merge – undersize commands: First, the size of each via is increased, until they overlap. We will first discuss different ways how this merging can be done, and later deal with the errors and side effects of that approach. Via simplification is usually done by combining the individual vias into a larger polygon that follows the outer boundary (or bounding box) of the via array. This is discussed at the end of this application note. solid vias in the real world, and we need to be carefuly with any via simplification that might change this current flow. Why do we care? Because that’s the behaviour of via arrays vs. This difference is important when metal layers are stacked with vias: the via array does not add cross section for the horizontal current flow, but a solid via does. That’s a difference between via arrays and the solid via blocks (“via bar”, “slot via”) that are also available in some technologies: a solid via can also take horizontal current, but the via array can only take vertical current. Via arrays consist of many parallel conductors in z-direction, where no current can flow in the x-y plane. ![]()
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